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AMMC-5033 17.7 - 32 GHz Power Amplifier
Data Sheet
Chip Size: 2730 x 1300 m (108 x 51.6 mils) Chip Size Tolerance: 10 m (0.4 mils) Chip Thickness: 100 10 m (4 0.4 mils) Pad Dimensions: 80 x 80 m (2.95 0.4 mils)
Description
Avago's AMMC-5033 is a MMIC power amplifier designed for use in wireless transmitters that operate within 17.7 GHz to 32 GHz range. At 25 GHz, it provides 27 dBm of output power (P-1dB) and 20 dB of small- signal gain from a small easy-to-use device. The device has input and output matching circuitry for use in 50 environments. The AMMC- 5033 also integrates a temperature compensated RF power detection circuit that enables power detection of 0.1 V/W at 22 GHz. For improved reliability and moisture protection, the die is passivated at the active areas.
Features
* * * * * Wide frequency range: 17.7 - 32 GHz High power: P-1dB @ 25 GHz = 27 dBm High gain: 20 dB Return loss: Input: -13 dB, Output: -20 dB Integrated RF power detector
Applications
* Designed for use in transmitters that operate in various frequency bands between 17.7 GHz and 32 GHz. * Can be driven by the AMMC-5040 (20-40 GHz) or the AMMC-5618 (6-20 GHz) MMIC amplifiers, increasing the power handling capability of transmitters requiring linear operation.
AMMC-5033 Absolute Maximum Ratings[1]
Symbol
Vd1,2 Vg1, Vgg Det Bias Id1 Id2 Pin Tch Tstg Tmax
Parameters/Conditions
Positive Drain Voltage Gate Supply Voltage Applied Detector Bias (Optional) First Stage Drain Current CW Input Power Operating Channel Temp. Storage Case Temp. Maximum Assembly Temp. (60 sec max)
Units
V V V mA dBm C C C
Min. Max.
7 -3 0.5 7 320 640 23 +150 -65 +150 +300
Second Stage Drain Current mA
Note: 1. Operation in excess of any one of these conditions may result in permanent damage to this device.
Note: These devices are ESD sensitive. The following precautions are strongly recommended: Ensure that an ESD approved carrier is used when dice are transported from one destination to another. Personal grounding is to be worn at all times when handling these devices.
AMMC-5033 DC Specifications/Physical Properties[1]
Symbol Id1 Id2 Vgg DETBias c1(ch-bs) c2(ch-bs) Parameters and Test Conditions First Stage Drain Supply Current (Vd1 = 3.5 V, Vg1 = Open, Vgg set for Id2 Typical) Second Stage Drain Supply Current (Vd2 = 5 V, Vg1 = Open, Vgg set for Id2 Typical) Gate Supply Operating Voltage (Id1(Q) + Id2(Q) = 780 (mA)) Detector Bias Voltage (Optional) First Stage Thermal Resistance[2] (Backside Temperature, Tb = 25C) Second Stage Thermal Resistance[2, 3] (Backside Temperature, Tb = 25C) Units mA V V V C/W C/W -0.75 Min. Typ. 280 500 -0.6 Vd2 31 19 -0.4 Max. 320
Notes: 1. Backside temperature Tb = 25C unless otherwise noted. 2. Channel-to-backside Thermal Resistance (ch-b) = 42C/W at Tchannel (Tc) = 150C as measured using infrared microscopy. Thermal Resistance at backside temperature (Tb) = 25C calculated from measured data. 3. Channel-to-backside Thermal Resistance (ch-b) = 24C/W at Tchannel (Tc) = 150C as measured using infrared microscopy. Thermal Resistance at backside temperature (Tb) = 25C calculated from measured data.
AMMC-5033 RF Specifications[4, 5]
Tb = 25C, Vd1 = 3.5 V, Vd2 = 5 V, Id1(Q) = 280 mA, Id2(Q) = 500 mA, Zo = 50
Lower Band Specifications (17.7 - 21 GHz) Unit
[5]
Parameters and Symbol Gain P-1dB P-3dB OIP3 Test Condition Small-Signal Gain Output Power at 1dB Gain Compression[6] Output Power at 3dB Gain Compression[6] dB dB dB
Mid Band Upper Band Specifications Specifications (21 - 26.5 GHz) (26.5 - 32 GHz) Max. Min. 17.5 25.5 Typ. 20 27 28 29.5 32 29 Max. Min. 16.5 25 Typ. 18.5 26.5 27 32 Max.
Min. 20 23.5
Typ. 22 25 27
Output Third Order Intercept dBm Point;[6]; f = 2 MHz; Pin = +2 dBm Input Return Loss[5] Output Return Loss
[5]
27
29
RLin RLout Isolation
dB dB dB
11.5 14
13.5 20 47
11 14
13 19 48
11 15
13 22 46
Min. Reverse Isolation
Notes: 4. Data measured in wafer form Tb = 25C. 5. 100% on-wafer RF test is done at frequency = 17.7, 21, 26.5 and 32 GHz. 6. 100% on-wafer test frequency = 17.7, 26.5 and 32 GHz.
2
AMMC-5033 Typical Performances
(Tb = 25C, Vd1 = 3.5 V, ID1 = 280 mA, Vd2 = 5 V, Id2 = 500 mA, Zin = Zout = 50 )
40 35 30 S21 (dB) 25 20 15 10 5 0 17 19 21 23 25 27 29 31 -80 33 -60 -25 -30 17 -40
S21 (dB) S12 (dB)
0
0 -5 RETURN LOSS (dB)
S22 (dB) S11 (dB)
-20 S12 (dB)
-10 -15 -20
19
21
23
25
27
29
31
33
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 1. Gain and reverse isolation
Figure 2. Return loss (input and output)
30
10
28 P-1 (dBm), P-3 (dBm) NOISE FIGURE (dB)
P-1 P-3
8
26
6
24
4
22
2
20 17
19
21
23
25
27
29
31
33
0 17
19
21
23
25
27
29
31
33
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 3. Output power at 1 dB and 3 dB gain compression
Figure 4. Noise figure
38 36 34 IP3 (dBm) 32 30 28 26 24 17 19 21 23 25 27 29 31 33
FREQUENCY (GHz)
Figure 5. Output 3rd order intercept point
3
AMMC-5033 Typical Performance Curves (Over Temperature and Voltage)
0.10
0.1
40
0.08 (DET_R)-(DET_O) (V) (DET_R)-(DET_O) (V)
30 GAIN (dB)
0.06 0.01 0.04
20
0.02 0.001 0 5 10 15 20 25 30 RF Output Power (dBm)
10
5V/0.5A 4V/0.5 3.5V/0.5A
0.00
0 17
19
21
23
25
27
29
31
33
FREQUENCY (GHz)
Figure 6. Linear and log detector voltage and output power, freq. = 22 GHz, Det_B = 5 V
Figure 7. Gain and Vd2 voltage, Vd1 = 3.5 V (constant)
30
0 -5 S11 and S22 (dB) -10 -15 -20 -25 -30 17
S11_85 C S11_25 C S11_-40 C S22_85 C S22_25 C S22_-40 C
28
P-1 (dBm)
26
24
5V/0.5A 4V/0.5 3.5V/0.5A
22
20 17
19
21
23
25
27
29
31
33
19
21
23
25
27
29
31
33
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Output power at 1 dB gain compression and Vd2 voltage, Vd1 = 3.5 V (constant)
Figure 9. Return-loss with temperature
4
30
30 25 Pout (dBm), PAE (%) 20 15 10 5 0 -30
Pout PAE Id
1200 1000 800 600 400 200 0 Id (mA)
28
P-1 (dBm)
26
24
85 C 25 C -40 C
22
20 17
19
21
23
25
27
29
31
33
-20
-10
0
10
20
FREQUENCY (GHz)
Pin (dBm)
Figure 10. Output power at 1 dB gain compression and temperature
Figure 11. Output power, PAE, and total drain. Current vs. input power at 25 GHz
50 40 30 S21 (dB) 20 10 0 -10 -20 -30 17 19 21 23
85 C 25 C -40 C
25
27
29
31
33
FREQUENCY (GHz)
Figure 12. Gain with temperature
5
Typical Scattering Parameters[1]
(Tb = 25C, Vd1 = 3.5 V, ID1 = 280 mA, Vd2 = 5 V, ID2 = 500 mA, Zin = Zout = 50 )
Freq [GHz] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 dB -10.7 -11.0 -11.4 -12.1 -15.3 -12.2 -14.0 -15.3 -17.6 -19.4 -18.6 -19.7 -24.5 -27.4 -30.6 -24.1 -21.2 -18.0 -15.5 -14.0 -13.3 -13.0 -12.9 -12.9 -13.0 -13.3 -13.9 -14.9 -15.8 -17.0 -19.1 -21.0 -20.5 -17.0 -14.9 -12.8 -10.7 -9.8 -9.1 -8.5 -8.6 -8.6 -8.0 -7.6 -6.0 -4.4 -3.5 -2.7 -1.8 -1.7 S11 Mag 0.29 0.28 0.27 0.25 0.17 0.25 0.2 0.17 0.13 0.11 0.12 0.1 0.06 0.04 0.03 0.06 0.09 0.13 0.17 0.2 0.22 0.22 0.23 0.23 0.23 0.22 0.2 0.18 0.16 0.14 0.11 0.09 0.1 0.14 0.18 0.23 0.29 0.33 0.35 0.38 0.37 0.37 0.4 0.42 0.5 0.6 0.67 0.74 0.81 0.83 Phase 173 167 161 153 140 149 143 139 138 145 152 141 134 159 -148 -121 -116 -116 -123 -133 -142 -151 -157 -163 -172 -178 174 165 155 140 113 75 30 -9 -31 -45 -58 -71 -77 -85 -92 -92 -92 -90 -87 -93 -98 -102 -111 -118 dB -51.1 -70.1 -46.6 -37.3 -22.6 -20.4 -20.5 -25.4 -33.1 -18.9 -18.2 -29.0 -15.4 0.9 12.7 22.6 28.8 28.7 26.4 24.7 23.4 22.4 21.5 20.8 20.3 19.9 19.7 19.5 19.4 19.3 19.1 18.6 18.1 17.2 16.2 14.6 12.1 7.7 1.9 -3.5 -9.2 -16.1 -23.2 -32.0 -31.7 -40.7 -46.2 -58.4 -46.4 -44.2 S21 Mag 0.003 0 0.005 0.014 0.074 0.096 0.095 0.053 0.022 0.113 0.123 0.035 0.169 1.107 4.316 13.52 27.62 27.25 20.92 17.18 14.82 13.2 11.9 10.97 10.36 9.895 9.691 9.457 9.384 9.247 8.972 8.519 7.989 7.281 6.44 5.378 4.014 2.42 1.238 0.671 0.347 0.157 0.069 0.025 0.026 0.009 0.005 0.001 0.005 0.006 Phase -163 79 -103 72 -31 144 79 -3 108 54 -37 -77 103 61 -8 -87 174 73 3 -53 -103 -151 164 121 79 37 -6 -49 -94 -141 171 121 69 14 -43 -104 -171 122 65 14 -41 -90 -134 -172 -148 -164 62 80 50 113 dB -95.1 -83.1 -74.5 -74.5 -80.3 -80.1 -80.3 -74.1 -81.4 -81.4 -81.3 -74.6 -81.3 -81.2 -74.6 -76.2 -74.7 -64.8 -64.3 -64.4 -69.7 -58.2 -63.3 -61.0 -66.1 -64.3 -63.1 -60.2 -61.9 -56.3 -57.7 -58.2 -56.0 -57.7 -59.0 -60.8 -62.9 -57.1 -61.0 -60.9 -67.6 -59.2 -61.0 -62.0 -64.6 -61.1 -102.4 -60.1 -59.2 -61.9 S12 Mag 1.77E-05 6.97E-05 1.89E-04 1.88E-04 9.66E-05 9.90E-05 9.68E-05 1.97E-04 8.52E-05 8.56E-05 8.59E-05 1.86E-04 8.65E-05 8.70E-05 1.86E-04 1.55E-04 1.84E-04 5.75E-04 6.08E-04 6.03E-04 3.27E-04 1.23E-03 6.80E-04 8.96E-04 4.97E-04 6.09E-04 7.00E-04 9.75E-04 8.00E-04 1.53E-03 1.31E-03 1.23E-03 1.59E-03 1.31E-03 1.12E-03 9.14E-04 7.13E-04 1.40E-03 8.94E-04 9.04E-04 4.15E-04 1.09E-03 8.95E-04 7.96E-04 5.91E-04 8.84E-04 7.57E-06 9.93E-04 1.10E-03 8.00E-04 Phase 128 76 81 69 -47 -126 94 35 -62 -162 151 178 -180 -20 152 144 -164 165 123 90 76 80 92 44 55 53 58 68 38 25 15 1 -15 -12 -36 -40 -31 -55 -61 -59 -65 -82 -75 -59 -123 -82 -171 176 -69 26 dB -0.5 -0.7 -1.2 -2.2 -2.4 -2.8 -4.0 -4.2 -3.5 -3.8 -4.4 -5.2 -6.3 -7.9 -10.1 -13.3 -20.5 -20.0 -19.4 -19.1 -18.7 -18.5 -19.0 -20.7 -21.8 -22.9 -22.9 -22.6 -22.1 -22.4 -24.9 -31.9 -31.4 -24.4 -20.0 -16.2 -13.1 -11.1 -10.1 -9.8 -9.7 -10.1 -10.6 -11.4 -12.3 -13.2 -14.2 -14.8 -14.7 -14.9 S22 Mag 0.95 0.92 0.87 0.78 0.76 0.73 0.63 0.62 0.67 0.64 0.6 0.55 0.48 0.41 0.31 0.22 0.09 0.1 0.11 0.11 0.12 0.12 0.11 0.09 0.08 0.07 0.07 0.07 0.08 0.08 0.06 0.03 0.03 0.06 0.1 0.16 0.22 0.28 0.31 0.33 0.33 0.31 0.29 0.27 0.24 0.22 0.2 0.18 0.18 0.18 Phase -26 -51 -76 -95 -112 -130 -146 -150 -166 177 161 146 131 115 100 86 76 133 130 135 133 129 124 119 122 131 135 142 136 125 117 126 -148 -141 -145 -152 -167 174 154 134 116 98 80 62 41 21 0 -27 -49 -77
Note: 1. Data obtained from on-wafer measurements.
6
Biasing and Operation
The recommended quiescent DC bias condition for optimum efficiency, performance, and reliability is Vd1 = 3.5 volts and Vd2 = 5 volts with Vgg set for Id1 + Id2 = 780 mA (no connection to Vg1). This bias arrangement results in default quiescent drain currents Id1 = 280 mA, Id2 = 500 mA. A single DC gate supply connected to Vgg will bias all gain stages. If operation with both Vd1 and Vd2 at 5 volts is desired, an additional wire bond connection from the Vg1 pad to Vgg external bypass chip capacitor (shorting Vg1 to Vgg) will balance the current in each gain stage. Vgg (= Vg1) can be adjusted for Id1 + Id2 = 780 mA. Muting can be accomplished by setting Vg1 and/or Vgg to the pinchoff voltage Vp. An optional output power detector network is also provided. Detector sensitivity can be adjusted by biasing the diodes with typically 1 to 5 volts applied to the Det- bias terminal. Simply connecting Det-Bias to the Vd2 supply is a convenient method of biasing this detector network. The differential voltage between the Det-Ref and Det-Out pads can be correlated with the RF power emerging from the RF output port. The detected voltage is given by: V = (Vref - Vdet) - Vofs Where Vref is the voltage at the DET_REF port, Vdet is a voltage at the DET_OUT port, and Vofs is the zero-input-power offset voltage. There are three methods to calculate Vofs: 1. Vofs can be measured before each detector measurement (by removing or switching off the power source and measuring Vref - Vdet ). This method gives an error due to temperature drift of less than 0.0002 dB/C. 2. Vofs can be measured at a single reference temperature. The drift error will be less than 0.25 dB. 3. Vofs can either be characterized over temperature and stored in a lookup table, or it can be measured at two temperatures and a linear fit used to calculate Vofs at any temperature. This method gives an error close to method #1. With reference to Figure 13, the RF input is DC coupled to a shunt 50 resistor but it is DC blocked to the input of the first stage. The RF output is DC blocked to the output of the second stage, however, it is DC coupled to the detector bias circuit. If the output detector is biased using the on-chip optional Det-Bias network, an external DC blocking capacitor may be required at the RF Output port. No ground wires are needed since ground connections are made with plated through-holes to the backside of the device.
Assembly Techniques
The backside of the AMMC- 5033 chip is RF ground. For microstripline applications, the chip should be attached directly to the ground plane (e.g., circuit carrier or heatsink) using electrically conductive epoxy.[1] For best performance, the topside of the MMIC should be brought up to the same height as the circuit surrounding it. This can be accomplished by mounting a gold plated metal shim (same length and width as the MMIC) under the chip, which is of the correct thickness to make the chip and adjacent circuit coplanar. The amount of epoxy used for chip and or shim attachment should be just enough to provide a thin fillet around the bottom perimeter of the chip or shim. The ground plane should be free of any residue that may jeopardize electrical or mechanical attachment. The location of the RF bond pads is shown in Figure 14. Note that all the RF input and output ports are in a Ground-Signal-Ground configuration. RF connections should be kept as short as reasonable to minimize performance degradation due to undesirable series inductance. A single bond wire is sufficient for signal connections, however double-bonding with 0.7 mil gold wire or the use of gold mesh[2] is recommended for best performance, especially near the high end of the frequency range. Thermosonic wedge bonding is the preferred method for wire attachment to the bond pads. Gold mesh can be attached using a 2 mil round tracking tool and a tool force of approximately 22 grams with an ultrasonic power of roughly 55 dB for a duration of 76 8 mS. A guided wedge at an ultrasonic power level of 64 dB can be used for the 0.7 mil wire. The recommended wire bond stage temperature is 150 2C. Caution should be taken to not exceed the Absolute Maximum Rating for assembly temperature and time. The chip is 100 m thick and should be handled with care. This MMIC has exposed air bridges on the top surface and should be handled by the edges or with a custom collet (do not pick up die with vacuum on die center.) This MMIC is also static sensitive and ESD handling precautions should be taken.
Notes: 1. Ablebond 84-1 LM1 silver epoxy is recommended. 2. Buckbee-Mears Corporation, St. Paul, MN, 800-262-3824
GND
DQ
Vd1
Vgg g
Vd2
DQ
DET. _ OUT
GND
D1 50 50 RF _ Input RF _ OUT
DET . _ BIAS Ref_ D2 50 250 50 1000 GND Vg1 Vgg Vd2 DQ GND DET . _ REF
Figure 13. AMMC-5033 schematic
Figure 14. AMMC-5033 bonding pad locations, dimensions are in microns
8
VD1, 280 mA 68 pF
VD2, 500 mA
VD2 VD1
RFInput
RFOutput
RFO
Notes: 1. 1F capacitors on gate and drain lines not shown required.
RFI
AMMC-5033
VD2 VGG 68 pF VEE
Figure 15. AMMC-5033 assembly diagram
Ordering Information:
AMMC-5033-W10 = 10 devices per tray AMMC-5033-W50 = 50 devices per tray
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright (c) 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-3935EN AV02-0682EN - September 5, 2007

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